A castellated via PCB features rows of holes drilled along the PCB’s edge. We plate these holes with copper and trim the board edges, which effectively cuts the edge hole size in half and leaves visible copper inside the plated holes along the PCB edge.
Designers generally equip module-type PCBs with castellated vias mainly to simplify soldering. As modular boards feature compact dimensions while supporting multiple functional needs, engineers typically place castellated vias along the PCB’s outermost edge. During contour routing, manufacturers route away half of each hole and retain only castellated vias on the PCB.
Advantages of Castellated Vias
A castellated module solders like a surface-mount part but connects like a through-hole one, which is why assembly houses treat it as the easy case: no connector to place, no separate reflow step, and a joint that can be inspected from the side. The advantages below follow from that single geometric fact.
- Short Signal Path: The connection runs straight from the module edge to the pad on the carrier board, with no connector body in between. That keeps the path short and the inductance low, although a castellation is not a shielded RF interconnect, and a design that needs controlled impedance or isolation still wants a connector.
- Durability: A soldered castellation has no moving contact and no shell to work loose, so it holds up better under vibration than a board-to-board connector in small IoT and wearable hardware.
- Reduced Production Costs: By soldering castellated via PCBs, you can avoid the use of expensive connectors, helping to lower production costs.
- Maximized Space Savings: A significant space-saving advantage of using castellated via PCBs is the ability to stack circuit boards vertically. This is particularly useful for ultra-compact wearable devices and sensor applications.
Manufacturing Process
The order of these steps matters as much as the steps themselves: the castellation only exists after the profile cut, and everything before it has to leave the plated wall intact.
- Design and Layout: Using professional software such as Altium or KiCad, castellated vias are precisely added to the edges of the PCB.
- Material Preparation: We select the substrate based on your requirements, ensuring the copper weight is suitable for the castellated via specifications.
- Drilling and Plating: We drill full-through holes along the PCB edges and plate the holes with copper to effectively establish the PCB’s castellated via structure.
- Imaging and Etching: The circuit pattern is transferred, and the excess copper layer is removed, leaving only your traces and copper pads.
- Solder Mask and Screen Printing: Solder mask application covers the board but stays off the castellation pads, so the copper that has to be soldered is left bare.
- Surface Treatment: Immersion gold or spray tin goes on next, to keep the copper from oxidizing before the module reaches the assembly line.
- Profile Routing: The outline is milled so the router takes away half of every edge hole, which leaves the plated wall open on the side. This step comes last for a reason: cutting before the finish would expose bare laminate where the castellation has to be soldered.
- Quality Control: Before packaging the goods, we perform a final inspection of the components to check the via dimensions and plating quality.
Material Selection
- Standard FR-4: Standard FR-4 is the most affordable and popular choice for electronic and hobbyist module applications.
- High-Frequency Materials: Designers select high-frequency substrates such as Rogers for RF, 5G, and other high-speed data designs to minimize signal loss across PCB vias.
- High-Temperature Materials: Materials such as polyimide provide the necessary heat resistance to prevent castellated via plating issues in printed circuit boards under harsh conditions.
- Metal Core Printed Circuit Boards (MCPCBs): Metal core PCBs use an aluminum or copper substrate to provide superior thermal dissipation for high-power LEDs or power conversion modules.
Quality Control and Process Challenges
Given the impact of via manufacturing on overall PCB performance, maintaining high quality is critical. Manufacturers implement several quality control measures:
- Optical Inspection: AOI checks the castellation outline and catches copper slivers the router may have left, and a microscope is used on a sample to look at plating coverage inside the half hole.
- Electrical Testing: A continuity test confirms that each castellation reaches the net it belongs to, and a micro-section on a coupon shows how thick the plating runs through the wall.
- Dimensional Accuracy: Regular measurements ensure that drilled and plated areas meet design tolerances. Any deviation can affect component placement and signal integrity.
Although the castellated via process offers numerous advantages, it also presents several challenges. These challenges include ensuring consistent plating thickness, preventing over-plating in unintended areas, and controlling thermal stress throughout the manufacturing cycle. Overcoming these challenges requires a robust process control framework and continuous monitoring throughout production.
PCB Castellated Via Design Guidelines
To maximize the benefits of castellated via technology, designers must follow a series of best practices and design guidelines. These recommendations help ensure that the final PCB meets the required performance standards while avoiding common pitfalls.
- Drill Size and Tolerances: Ensure that drill sizes are compatible with the intended plating process. Precise drilling is critical for achieving consistent results.
- Plating Thickness: Determine the optimal plating thickness for the castellated vias based on the application’s electrical and mechanical requirements. Plating that is too thin may compromise conductivity, while plating that is too thick may lead to manufacturing challenges.
- Layer Stackup: Settle the layer configuration before drilling. Whether a castellation has to reach an inner plane is a stackup decision, not one the router can fix later.
- Thermal Management: Consider the PCB’s thermal distribution, particularly in high-power applications. An appropriate via design aids in heat dissipation and reduces thermal stress on critical components.
- Signal Routing: Optimize the layout to minimize interference and ensure that vias do not introduce unwanted parasitic elements that could compromise signal integrity.
Future Trends and Innovations
Demand for denser module boards keeps pushing the castellation process, and the changes are coming from a few directions.
- Plating Control: New deposition methods give tighter control over plating thickness inside the half hole, which is the parameter that decides whether the castellation survives reflow.
- Integrating with 3D PCB Design: Modern PCBs are evolving toward three-dimensional structures, and designers can combine castellated via technology with 3D interconnects to develop more compact, high-efficiency layouts.
- Simulation: Tools that model the castellation as the open half cylinder it is, rather than as a full via, give a closer estimate of the impedance step at the module edge.
- Focus on Sustainability: With the growing emphasis on sustainable manufacturing practices, future innovations may focus on reducing material waste and energy consumption during profile routing.
Summary
A castellation is a plated through hole that has been cut in half at the profile stage, and the whole idea is in that sentence. What it buys is a module that can be placed and reflowed like any other surface-mount part while still presenting a solderable copper wall along its edge. What decides whether it holds up is plating thickness through that wall, the quality of the cut, and the surface finish applied before the cut.
For a designer the actionable points are narrow: keep the castellation pitch compatible with the module footprint, specify plating thickness instead of leaving it to the shop, and settle the surface finish before the profile step is planned. Get those three right and the board edge stops being a source of assembly defects.
