PCB routing is the process of laying out the paths that connect components and carry electrical signals. By the time it starts, placement and stackup are already fixed, so routing is where the design either holds its margins or loses them. It is also the longest step in most projects, and the one that decides whether a board passes EMC testing or comes back for a respin. The same rules apply to single-sided, double-sided, and multilayer boards.
Basic Principles of PCB Routing
Maintaining Signal Integrity
Signal integrity fails when the waveform that reaches the receiver no longer matches what the driver launched. On a routed board the usual causes are reflections from impedance discontinuities, crosstalk coupled from neighboring traces, and ground bounce through a broken return path. All three are cheaper to prevent before the first trace is drawn than to chase on a failing prototype.
Adhering to Impedance Matching Rules
Impedance has to be settled before routing starts, because it is a property of the trace geometry and the dielectric around it, not something the router can correct afterwards. A 50 Ω single-ended net and a 90 Ω differential pair need different widths and spacing, and both are fixed by the stackup. Every point where the target is missed reflects part of the signal back to the driver.
Consider Manufacturing Processes During Design
Routing rules only work if the fabricator can hold them. Minimum trace width and spacing, annular ring, and drill size come from the shop’s process capability rather than from what the EDA tool allows: 3 mil is reachable on 18 µm base copper, but the same shop needs 4.5 mil of outer-layer width on 1 oz. Design to those numbers with a margin for etch tolerance, and the panel comes back right the first time.
PCB Routing Layout Strategies
Pre-Layout Preparation
Routing cannot rescue a bad starting point. Two decisions made before the first trace matter more than anything the router does afterwards: how much power the board dissipates, and which packages that power has to reach.
Determine the Circuit’s Power and Thermal Analysis
Power analysis comes first. Add up the dissipation of every regulator, driver, and processor, then map where that heat lands on the board outline. The result is a thermal map, and it drives placement: hot parts get the copper and the airflow, sensitive parts get distance.
Keep crystals, voltage references, and sensors out of the hot corner, and give the hot parts a short path to the copper that spreads their heat. Where copper alone is not enough, the design adds heat sinks, fans, or thermally conductive interface material, but those are the expensive answers and belong after placement has done what it can.
Selecting Appropriate Components and Packages
Package choice sets the floor on everything else: it fixes the pin pitch, the escape routing that pitch allows, the number of layers needed to break the part out, and how much copper it can dump into the board. A component that is 20% cheaper but needs two more layers is not cheaper.
Picking the smallest package saves board area, but it costs placement yield and leaves less copper to spread heat, and a fine-pitch part that saves 5 mm of length can add a whole layer to escape. Availability and second-source status matter as much as the datasheet, because a part on allocation stops a build long before its electrical performance does.
Basic Principles of Layout
PCB layout has one job: put every part where its signals, its heat, and its return current can all be handled without fighting each other. Four rules cover most of it.
Follow the Signal Flow
Draw the main signal paths before moving anything. Start at the connector or the transceiver and follow the path to the far end, placing parts along it so the trace runs straight and short. Keep analog, digital, and RF sections in their own areas, meeting only where a converter or a connector forces them to.
Consider Intercomponent Interference
Interference is a placement problem before it is a routing problem. Clock oscillators, switching regulators, and high-current loops radiate from where they sit, so distance and orientation do more than shielding. EMC is designed in by keeping loop areas small and return paths short, not by adding a can over the noisy part at the end.
Reserve Routing and Test Paths
Leave more routing channels than the current design needs. Dense areas are where the last few nets force vias, longer detours, and crosstalk, and where a later revision has no room to move. Add test points on every net that has to be probed, with a ground via beside each one, or fault diagnosis turns into guesswork.
Layout Optimization Methods
Two optimizations pay for themselves on almost every board.
- Shorten routes by assigning layers deliberately. Give each signal group its own layer and reference plane, keep related nets on the same layer so they do not need vias, and route adjacent signal layers orthogonally: traces that cross at right angles couple far less than traces that run parallel on facing layers. A stackup design with a ground plane between two signal layers removes the problem entirely, which is why the extra layer is often worth it.
- Place parts in the order the signal travels. Power input, conversion, and decoupling first, then the digital core, then the interfaces at the board edge, so each group lands next to the nets it talks to. Auto-placement optimizes for area and connectivity and knows nothing about return paths or thermal spread, so treat what it produces as a starting point and plan to spend most of the placement time moving it.
PCB Routing Details
Determining Trace Width and Spacing
Once placement is fixed, two numbers decide whether the board works: how wide each trace is, and how far it sits from its neighbors.
Determining Trace Width Based on Current Requirements
A narrow trace dissipates more power per unit length and runs hotter, so the current it has to carry sets its minimum width. The industry relationship is the IPC-2221 curve fit:
I = k × ΔT0.44 × A0.725, where I is current in amps, ΔT is the allowed temperature rise in °C, A is the copper cross-section in square mils, and k is 0.048 for an external layer or 0.024 for an internal one.
Solve that for area, divide by the copper thickness, and you have the required width.
In practice, most designers skip the algebra and read the same relationship off a fabricator’s current-carrying table or an EDA calculator. As a check: 2 A at a 10 °C rise on 1 oz copper needs about 42 square mils of cross-section, which on an external layer works out to roughly 31 mil (0.79 mm) of width. Add 20% on top for production margin.
The internal-layer penalty is the part designers forget. The same 2 A needs about 2.6 times the copper area once the trace is buried between dielectrics, so a width that works at 31 mil on the top layer becomes 80 mil (2.0 mm) on an inner one.
Adhering to Minimum Spacing Requirements for the Manufacturing Process
Spacing is the other half of the rule, and on most boards it is set by the fabricator rather than by the standard. Shops hold 6 mil (0.15 mm) as routine, 4 mil (0.10 mm) once the base copper is thin, and 3 mil (0.075 mm) at the fine-line end, with cost climbing at each step because the process window narrows and yield drops.
Which number applies depends on two things: what the shop can hold, and what the voltage demands. Designers weigh three factors when setting it:
- Insulation layer thickness, meaning the dielectric between the conductors
- Operating voltage, including the transients the board will see
- Manufacturing tolerances, mainly etch and layer registration
Spacing must be large enough to prevent a short or an arc at the worst-case voltage. On most low-voltage boards that floor sits well below the fabrication minimum, so the shop’s capability is what usually decides. Set the spacing in the design rules so violations are flagged as they happen, and add margin for the one thing the rule cannot see: a fabricator running at the edge of its process.
Summary
PCB routing turns a schematic into a manufacturable board, and almost every performance problem found on the bench traces back to a decision made here. Autorouters have improved, but none of them knows the intent behind a net, so the judgment still sits with the engineer.
