IC Package Types and Semiconductor Packaging Process

IC packaging is the step between a finished wafer and a part that can go on a board. After the wafer is probed and diced, each good die is mounted, connected, and sealed, and that package is what placement, reflow, and the PCB layout all have to handle.

What it produces is what the board team has to design around: a footprint, a pitch, a thermal path, and an inspection problem.

Which type a design gets is usually the chip vendor’s decision. The board team inherits the footprint, the pitch, and the process window.

IC PCB

What Is IC Packaging?

Packaging starts with a bare die: silicon with pads on one face and nothing else. The die is mounted on a substrate or lead frame, connected by wire bonding or flip-chip bumps, and encapsulated in plastic, ceramic, or metal.

The finished part has to do four jobs:

  • Protect the die from damage and contamination
  • Bring its connections out to a pitch the PCB can route
  • Carry heat from the die to the board or the air
  • Give the placement machine a body to pick and place

Types of IC Packages

Three classifications are in common use, and they are independent. A plastic BGA is a plastic package, a surface-mount part, and a ball-array structure at the same time. Reading the three together tells you how a device constrains the board.

1. By Packaging Material

Metal Packages

Metal packages give the best mechanical strength and thermal path of the three, because the case is the heat spreader. The cost keeps them out of most commercial work. They appear in power devices, in hermetic military and aerospace parts, and in anything meant to survive a harsh environment.

Ceramic Packages

Ceramic holds its dimensions and insulation over temperature, and it is hermetic, so moisture cannot reach the die. That is why it appears in aerospace, in industrial electronics, and in parts meant to work for decades. It is also the natural substrate for high-frequency and high-power work, at a price that rules out consumer volume.

Plastic Packages

Plastic is the default for consumer electronics and, by volume, most of the market. The advantages are cost, a simple molding process, and reliability that covers almost everything:

  • Low manufacturing cost
  • Simple, high-volume production
  • Reliability adequate for consumer and most industrial use
  • Wide range of body sizes and pin counts

What plastic gives up is hermeticity. The molding compound absorbs a little moisture and passes it slowly, which is why plastic parts carry a moisture sensitivity level and a floor life.

2. By Connection Method

Through-Hole Package (PTH)

Through-hole parts have leads that pass through drilled holes and are soldered on the far side. DIP is the standard example, on a 2.54 mm pitch unchanged in fifty years.

DIP package with through-hole leads on 2.54 mm pitch, next to its PCB footprint
  • Mechanical connection strong enough to survive connectors being plugged in beside it
  • Suited to high-reliability and socketed applications
  • Easy to hand-solder, replace, and probe

The cost is board area: 2.54 mm pitch buys about a tenth the pin density of a fine-pitch surface-mount part, and every pin needs a hole through every layer. Through-hole has left consumer designs and holds on in power, connectors, and parts that get replaced in the field.

Surface Mount Package (SMT)

Surface-mount parts are soldered directly to pads on the board surface, with no holes. Common families and their pitches:

  • SOIC: 1.27 mm
  • TSSOP: 0.65 mm
  • QFN: 0.5 to 0.8 mm, with an exposed thermal pad underneath
  • QFP: 0.3 to 1.0 mm
  • BGA: 0.8 to 1.27 mm, finer on memory and mobile parts
  • CSP: 0.3 to 0.5 mm

That process is what SMT assembly is built around: paste printing, placement, reflow, inspection. That pitch list is also the list of process limits; below about 0.5 mm, stencil aperture and paste release decide yield as much as the placement machine.

PCB SMT

3. By Package Structure

QFP and BGA both appear in the surface-mount list. They are worth separating by structure, because structure, not mounting method, is what changes the routing.

QFP (Quad Flat Package)

QFP brings leads out on all four sides, gull-wing formed to sit flat on the pads. A 0.5 mm pitch QFP puts 208 leads on a 28 mm body. The joints are visible, so visual and AOI inspection work, and almost any assembly house can run the process. Microcontrollers, industrial parts, and automotive control ICs are still largely QFP.

BGA (Ball Grid Array)

BGA moves the connections underneath as a grid of solder balls. That buys pin density a leaded package cannot reach: hundreds of balls under a body a QFP of the same size could not match, with lower inductance and a better thermal path through the board.

It also removes the ability to look at the joint. Balls are inspected by X-ray, and the escape routing under the array is what pushes a board toward finer lines and more layers. More on that in BGA packaging and miniaturization.

CSP (Chip Scale Package)

CSP is defined by size. JEDEC puts the limit at a package area no more than 120% of the die area, which leaves almost no room for a substrate overhang or molding margin. A ball pitch of 0.5 mm or below usually follows.

The gain is board area and electrical performance: the die-to-board interconnect runs a few hundred micrometers instead of several millimeters. The cost is thermal. There is almost no body to spread heat into, so a CSP depends on the copper underneath, which makes thermal via design a board decision rather than a package one. Phones, memory, and wearables run on CSP; power devices rarely do.

What the Package Asks of the PCB

The package type fixes the constraints that matter before any routing starts:

  • Pitch and fanout. Above 0.8 mm a trace can escape between pads. Below 0.5 mm it usually cannot, and the design moves to a via directly under each ball, which needs filled and capped vias.
  • Layer count. A ball array with hundreds of connections cannot escape on two layers, and the inner rows have to reach the surface through vias. That is what makes BGA and CSP work an HDI exercise.
  • Thermal path. QFN and CSP have little body to spread heat, so the copper under the part and the thermal vias through it carry the load. QFP and DIP dissipate through their leads.
  • Inspection. Visible leads can be inspected optically. Balls and bottom pads cannot, so those parts move to X-ray.

Summary

IC packaging turns a die into a component: it protects the silicon, brings its connections out to a usable pitch, and gives it a thermal path and a body to place. Material, mounting method, and structure are independent classifications, and a part sits at one point on each. What reaches the PCB is the consequence: pitch sets the fanout, the ball array sets the layer count, the exposed pad sets the thermal vias, and the hidden joint sets the inspection method. Where the package meets the board most directly is the IC carrier PCB, which carries its own process constraints.

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